Wireless assisted global navigation satellite systems (GNSS) with emerging enhanced 911 (E911) compliance standards require reduced acquisition time in GNSS reception. A user's location information needs to be accurately communicated in the shortest possible time to emergency support providers. If the location data is not accurate, emergency dispatchers may experience difficulty in routing 911 calls to the appropriate center. Mobile phones also need to be operable indoors and in urban canyons. Typical GNSS systems also need to have the capability to handle weak signals and respond with both speed and location accuracy. For example, E911 compliance requires that the object be identified within 125 meters and within a 5 second span in most instances.
The conventional method to acquire satellite signal is through the use of multiple hardware blocks. Time to first fix (TTFF) performance is dependent on the correlation acquisition process. For example, incoming GNSS signals from twelve respective satellites are channeled to twelve hardware blocks partitioned in a correlator. The twelve hardware blocks then perform the correlation exercise in parallel. The above conventional approach faces significant challenges such as high time to first fix and where a larger number of correlators are provided, the conventional approach increases the size of the correlator device and hence the overall silicon real estate of a receiver in a GNSS system. There is a strong industry move towards GNSS integration in automotive and hand-held applications. These applications demand the GNSS system have a small form factor. For achieving low TTFF, GNSS systems require a very large number of correlators to simultaneously search the code shifts and frequency bins to acquire the satellite signal. The area and power numbers increase drastically with the number of acquisition correlators. This poses a great challenge for hand-held GNSS applications.
Therefore, there is a long felt but unresolved need to provide an implementation of a GNSS receiver that achieves reduced TTFF without a significant increase in gate count of the hardware.